Simon's Law of Crystal-Electromagnetic Scaling

1.1 The Moore's Law Trajectory

In 1965, Gordon Moore observed that the number of components on an integrated circuit was doubling annually, projecting this trend would continue for at least a decade. He later revised this to a doubling every two years.^[1] This observation, elevated to "law" status by the industry, has held remarkably true. The Intel 4004 processor in 1971 contained 2,300 transistors; by 2025, NVIDIA's GB202 GPU contains over 92 billion. That represents a 40-million-fold increase in 54 years.

However, the trajectory is bending. The International Technology Roadmap for Semiconductors disbanded in 2016 after its projections showed no further improvements via traditional scaling. Intel acknowledged in 2015 that its cadence had slowed to two and a half years. The industry consensus, reinforced at the 2025 Nature Conference on Novel Materials and Devices for the Post-Moore Era in Beijing,^[9] is that silicon's geometric scaling is approaching a practical terminus.

1.2 The Five Barriers

Silicon transistor scaling faces five interconnected barriers that collectively define the Moore's Law ceiling:

• Quantum Tunneling

  Below 3 nm gate lengths, electrons tunnel through the channel barrier, destroying reliable switching.

• Leakage Current

  Even in the off state, current leaks through atomically-thin gate oxides — wasting power, generating heat.

• Thermal Dissipation

  Power density already exceeds 100 W/cm² in advanced processors. Cooling cannot keep up with density.

• Fabrication Complexity

  EUV machines cost > $200M each; high-NA EUV approaches $400M. Capex per node doubles every ~4 years.

• Dennard Collapse

  Voltage scaling stalled in 2004. Density gains no longer translate to proportional efficiency gains.

These barriers are not engineering problems that incremental improvements can solve. They are physical limits rooted in quantum mechanics and thermodynamics. A fundamentally different approach is required.

1.3 The Thesis

This paper proposes that the answer lies not in shrinking transistors further, but in changing what they are made of and how they are controlled. Specifically, we propose replacing silicon channels with crystalline semiconductor materials and replacing voltage-based gating with electromagnetic-piezoelectric coupling. This combination creates a scaling vector that is independent of physical dimensions.

We formalize this as Simon's Law of Crystal-Electromagnetic Scaling:

P(t) = P₀ × (d₃₃ × ECCF)^(t/T)

2.1 Crystal Lattice Advantages Over Silicon

Silicon's dominance in semiconductors stems from its abundance, well-understood processing, and moderate electron mobility of approximately 1,400 cm²/V·s. However, silicon lacks two properties that are critical to our thesis: piezoelectricity and high crystallographic order at extreme scales. Crystalline alternatives — GaN (2,000 cm²/V·s), InGaOₓ, ZnO, and 2D MoS₂ — provide both, along with bandgaps and breakdown fields that silicon cannot match.

2.2 Piezotronics: Crystal Fields as Gate Signals

The field of piezotronics, introduced by Professor Zhong Lin Wang at Georgia Institute of Technology in 2007,^[2] established that the piezoelectric potential (piezopotential) generated inside non-centrosymmetric crystals can function as a transistor gate signal. This eliminates the need for an external voltage source to control current flow — the crystal lattice itself becomes the gate.

2.3 Photonic + EM Crystal Coupling

This concept draws on established physics from three domains: piezoelectricity (Curie brothers, 1880), electromagnetic resonance in crystals (used in quartz oscillators since the 1920s), and photonic crystal computing (emerging since 2006). Our contribution is unifying these into a single transistor gating paradigm — where an applied EM field, resonating with the crystal lattice, modulates carrier flow without geometric scaling.

3.1 The Law

Simon's Law of Crystal-Electromagnetic Scaling states:

"As crystal lattice purity and electromagnetic coupling efficiency improve, transistor switching performance scales proportionally to the product of the piezoelectric coefficient and EM coupling factor of the crystal medium, independent of physical transistor size."

3.2 Mathematical Formulation

The law is expressed as:

P(t) = P₀ × (d₃₃ × ECCF)^(t/T)

3.3 The EM-Crystal Coupling Factor (ECCF)

ECCF is the novel metric at the heart of Simon's Law. It is defined as:

ECCF = (d₃₃ × E₀ × Q) / (δ × f)

ECCF captures the essential physics in a single number: how much of the incoming EM energy actually converts to usable gate potential. Values below 0.3 indicate poor coupling; 0.3–0.7 indicates moderate coupling with practical potential; above 0.7 indicates high-efficiency coupling suitable for transistor gating.

Critically, ECCF can be improved through three independent pathways: better crystal purity (increasing d₃₃ and Q), stronger EM sources (increasing E₀), and optimized crystal geometry (tuning δ to maximize resonance). None of these pathways require physical miniaturization.

3.4 Why This Differs from Moore's Law

Moore's Law scales performance by making transistors physically smaller. When transistors cannot get smaller, Moore's Law stops. Simon's Law scales performance by improving the electromagnetic-crystal interaction. Since crystal purity, EM source technology, and resonance engineering are all active areas of improvement with no known physical ceiling, the scaling vector remains open.

Simon's Law is not speculative. It is grounded in published, peer-reviewed experimental results spanning three converging research domains.

Simon's Law and the Crystal-EM Hybrid approach exist within a competitive landscape of post-Moore technologies. The following analysis positions our thesis relative to each.

The Crystal-EM Hybrid approach is at an earlier stage than GAA or 3D stacking, but it offers a unique advantage: it is the only approach whose scaling mechanism is entirely decoupled from physical dimensions. GAA still requires smaller transistors. Carbon nanotubes still require precise nanoscale alignment. Photonic computing requires nonlinear optical materials that remain expensive. Simon's Law scales with crystal quality and EM engineering — both of which are improving on independent, well-funded trajectories.

To model, test, and communicate the Crystal-EM Hybrid thesis, we developed CrystalSim — an interactive web-based semiconductor simulator. CrystalSim is the first platform to unify crystal material properties, piezoelectric field simulation, electromagnetic coupling modeling, and scaling law projection in a single tool.

• 01Mission Control Dashboard
• 02Crystal Lab
• 03Transistor Simulator
• 04Piezoelectric Field Simulator
• 05Electromagnetic Coupling Engine
• 06Scaling Laws Dashboard
• 07Research Library
• 08Hybrid Designer

CrystalSim runs entirely in the browser with no backend dependencies. All physics calculations execute client-side using simplified but physically grounded models derived from the experimental data presented in Section 4.

The Crystal-EM Hybrid thesis is currently at Technology Readiness Level 2–3 (concept formulated, computational models developed). The following roadmap outlines the path to higher TRL:

1. Phase 1Computational Modeling

   TRL 2–3

   Concept formulated; CrystalSim implements the physics models. Current state.

2. Phase 2Materials Characterization

   TRL 3–4

   Partner with thin-film growth facility to verify ZnO, PZT, and InGaOₓ d₃₃ / mobility predictions.

3. Phase 3Single-Device Prototype

   TRL 4–5

   Fabricate a single Crystal-EM transistor with EM-coupled gating and benchmark vs. silicon.

4. Phase 4Integrated Demonstrator

   TRL 5–6

   Multi-device array showing density and efficiency advantages over a silicon control circuit.

5. Phase 5Publication & Commercialization

   TRL 6–7

   Peer-reviewed journal publication; foundry licensing; open-source CrystalSim advanced edition.

We are not claiming that Crystal-EM Hybrid transistors will replace silicon tomorrow. We are claiming that the physics support a new paradigm, that the experimental evidence is sufficient to justify serious research investment, and that Simon's Law provides the mathematical structure needed to plan, predict, and optimize that research.

1. [1]Moore, G.E. (1965). Cramming More Components onto Integrated Circuits. Electronics Magazine, 38(8).
2. [2]Wang, Z.L. (2007). Nanopiezotronics. Advanced Materials, 19(6), 889–892.
3. [3]Chen, A. et al. (2025). A Gate-All-Around Nanosheet Oxide Semiconductor Transistor by Selective Crystallization of InGaOₓ. 2025 Symposium on VLSI Technology and Circuits.
4. [4]Xu et al. (2026). Single-Crystal PZT-Driven Organic Piezo-Phototronic Adaptive Transistors. Advanced Science.
5. [5]Zhang, X. et al. (2014). Piezoelectricity of single-atomic-layer MoS₂. Nature Nanotechnology.
6. [6]Goodarzi & Ghanaatshoar (2018). Coherent all-optical transistors based on photonic crystal structures. Scientific Reports.
7. [7]Skoltech & IBM (2021). Ultra-energy-efficient optical switch. Nature Photonics.
8. [8]Wang, L. & Wang, Z.L. (2023). Advances in piezotronic transistors and piezotronics. Nano Energy.
9. [9]Nature Conference on Novel Materials and Devices for the Post-Moore Era (2025). Beijing, China. Nature.
10. [10]Shalf, J. (2020). The future of computing beyond Moore's Law. Philosophical Transactions of the Royal Society A, 378(2166).