// module M2 · transistor sim

Transistor Sim

Simplified physics

Architecture-level simulation across 5 device topologies — from the 1971 planar FET to the Crystal-EM hybrid thesis.

// architectures · 5 topologies

// device cross-section

Planar FET

Si baseline · 1971–2011

The 40-year silicon workhorse — flat channel, simple gate.

// configuration

Channel MaterialSi

Gate Length3 nm

Channel Width50 nm

Operating Voltage0.7 V

Temperature300 K

// engineering output

Live curves from the canonical material database — channel: Si, architecture: planar, compact model: BSIM4.

// I_D vs V_DS family

Linear (triode) → saturation; dotted lines = Si baseline at same node.

model: BSIM4

// results · live simulation

Threshold Voltage

1.0× Si

0.43 V

ON/OFF Ratio

1.0× Si

3.16×10⁶

Subthreshold Swing

1.0× Si

69.0 mV/dec

Leakage Current

1.0× Si

25.5 nA

Switching Frequency

1.0× Si

0.27 GHz

Power per Switch

1.0× Si

0.52 fJ

// benchmarks · saved configurations

No benchmarks yet. Run a comparison to start building your comparison ledger.