§ /for/manufacturers
Process Compatibility for Crystal-EM Transistors
Where the Crystal-EM thesis intersects existing CMOS, GaN, and BEOL flows — what's drop-in, what needs new tooling, and which insertion points are realistic in a 3-year horizon.
§ compatibility matrix
| Component | Si CMOS | GaN-on-Si | BEOL | Special tooling |
|---|---|---|---|---|
| GaN channel | partial | yes | no | MOCVD |
| PZT gate | thermal budget issue | possible | yes | Sol-gel / PLD |
| EM coupler | yes | yes | yes | Standard metal |
| HfO₂ buffer | yes | yes | yes | ALD |
| TiN gate | yes | yes | yes | PVD / ALD |
§ tooling cost vs EUV
| Technology | CapEx | Reference |
|---|---|---|
| EUV lithography (3 nm node) | $180–250M / scanner | ASML NXE:3600D |
| MOCVD GaN-on-Si | $8–15M / reactor | Veeco / Aixtron |
| PZT sol-gel + RTA | $1–3M / line | Existing thin-film tools |
| Standard BEOL metal | amortized | Already on every fab floor |
Crystal-EM tooling reuses existing GaN/thin-film lines. No EUV-class capital required for the analog/RF insertion path.
§ realistic insertion roadmap
Year 1
Low — uses existing GaN-on-Si lines
Analog / RF discrete (GaN HEMT + EM coupler)
Year 2–3
Medium — thermal budget integration
Mixed-signal (PZT-gated SoC blocks)
Year 4–6
High — yield + density open
Digital logic insertion (selected blocks)
Year 7+
Speculative — requires Phase-3 prototype data
Full CMOS replacement in target nodes
§ open questions for foundry partners
- 1. What is the maximum thermal budget your line tolerates after M1 metallisation? (PZT crystallisation needs 600–700 °C RTA.)
- 2. Is your GaN-on-Si line qualified for < 200 nm gate length, or limited to power-electronics geometries?
- 3. Do you have BEOL ferroelectric experience (HfZrO, PZT, or similar)? At what wafer size?
- 4. Acceptable defect density target for an analog/RF prototype run (parts/cm²)?
- 5. Is there interest in a multi-project wafer (MPW) shuttle for a 4–8-mask test chip?
§ foundry inquiry
Talk to the project lead
NDA-friendly. Replies within 5 business days. The form below opens your mail client with a pre-filled template addressed to research@crystalsim.io.