Mission Control
Live status of the Crystal-EM thesis.
Transistor Scaling — 1971 → 2035
Logarithmic transistor count per leading-edge processor, with the Crystal-EM hybrid projection overlaid.
Silicon is hitting a wall.
Silicon transistors are hitting quantum tunneling limits at sub-3nm geometries. Heat dissipation, leakage current, and fabrication costs are making traditional scaling unsustainable — each node yields diminishing performance gains for an order-of- magnitude increase in capex.
Our thesis: crystalline materials with electromagnetic coupling can create a new scaling paradigm — one that doesn't depend on shrinking the transistor.
Jump into a module
Crystal Lab
Explore lattice structures, mobility, bandgap, and piezoelectric coefficients across 8 candidate materials.
Transistor Sim
Model crystal-based transistor architectures and compare switching characteristics against silicon.
Scaling Laws
Project performance trajectories beyond Moore's Law with the crystal-EM hybrid model.