§ /for/investors
An Independent Research Program with Open IP
Pre-validation thesis seeking lab partnership. Capital-efficient phased plan. The simulator and material database are public; the next step is silicon.
§ market context
Semiconductor TAM (2030)
>$1.0T
WSTS / SEMI projections
Foundry CapEx (2024)
$185B
SEMI World Fab Forecast
EUV scanner cost
$180–250M
ASML NXE:3600D
The end of geometric scaling is creating an opening for non-geometric architectures. Photonics, quantum, neuromorphic, and analog/RF alternatives have all attracted serious capital in the last 36 months.
§ comparable bets
| Company | Capital raised | Thesis |
|---|---|---|
| Lightmatter | $270M+ | Photonic compute |
| Cerebras | $720M+ | Wafer-scale logic |
| Ayar Labs | $370M+ | Optical interconnect |
| PsiQuantum | $1.0B+ | Photonic quantum |
| Rain AI | $33M+ | Analog neuromorphic |
Public sources: Crunchbase, PitchBook, company press releases (2021–2025).
§ phased plan
Phase 1 — Today
~$0complete
Public simulator, 8-material database, validation pages, MIT-licensed code.
Phase 2
~$500K12–18 months
Lab partnership for material validation: PZT-on-GaN stack characterisation + 2DEG mobility under piezo strain.
Phase 3
~$5M18–30 months
Single-device prototype: GaN/PZT hybrid HEMT in a partner foundry MPW. Measure I-V, f_T, reliability vs simulator predictions.
Phase 4
~$25M30–60 months
Multi-device array, IP filing, design-kit packaging, first commercial-grade test chip in a target analog/RF block.
§ the risk we won't hide
Why this could fail
Honest list. If any of these moves a thesis from "interested" to "deal-breaker", we'd rather know now.
PZT thermal compatibility
PZT crystallisation requires 600–700 °C RTA. This conflicts with most CMOS BEOL thermal budgets (≤ 400 °C). Mitigation paths (HfZrO substitution, BEOL-only integration) are unproven at scale.
EM crosstalk at scale
Single-device EM coupling is well-modelled. Array-level crosstalk and substrate coupling at GHz frequencies is not — this is a genuine open question that only silicon will answer.
Yield and defect density
GaN-on-Si defect densities are an order of magnitude worse than mature Si CMOS. Hybrid stacks compound this. A commercial digital insertion is unlikely until defect engineering matures.
Independent-researcher execution risk
The program is led by a single independent researcher pre-Phase-2. Lab partnership and team expansion are prerequisites for credible Phase-3 execution.
Competing roadmaps
TSMC N2/A14, Intel 14A, and IBM 2nm continue to deliver per-node improvements. The window for a non-geometric scaling alternative is open but not infinite.
§ investor contact
Request the data room
Engineering Brief is public at /brief. Phase-2 lab plan, projected milestones, and IP strategy available under NDA. The form opens your mail client with a pre-filled template addressed to research@crystalsim.io.