// engineering brief · v1.0
Engineering Brief: The Crystal-EM Hybrid Thesis
Post-Moore Scaling: A Quantitative Framework
Problem Statement
The end of geometric scaling
Per the IRDS 2024 More Moore roadmap, lateral pitch scaling for advanced CMOS has effectively stalled below the 12 nm CPP regime, and effective channel length L_eff has been pinned near 12–14 nm since the N5/N3 nodes. Industry-reported I_eff/W gains node-over-node have collapsed from ~30 % per generation in the 2010s to <8 % between N3 and N2, while wafer ASPs have grown roughly 1.5× per node. The performance/$ trajectory that defined two decades of compute scaling has flattened into a plateau.
The dominant loss mechanisms are well characterized: parasitic R_ext from contact and source/drain extension resistance now consumes >50 % of the total drive at sub-3 nm widths (Khan et al., IEDM 2022), and Boltzmann-limited subthreshold swing forces a hard floor at 60 mV/dec at 300 K. Dennard scaling — which guaranteed constant power density under geometric shrink — was already broken at 90 nm (Frank/Nowak, Proc. IEEE 2001); we have been engineering around its corpse with FinFET, GAA nanosheet, and backside-power workarounds.
The result: industry roadmaps (TSMC A14, Intel 18A, Samsung 2 nm, IBM 2 nm Nanosheet) all converge on the same architecture — stacked Si/SiGe nanosheets with backside power — within ~10 % of each other on every metric. Geometric scaling has nearly converged on its physical asymptote, and incremental material substitutions (2D channels, alternative oxides) buy single-digit percent improvements. A new degree of freedom is required, not another node.
| Node | Perf/W (rel.) | Cost (rel.) | CPP (nm) |
|---|---|---|---|
| TSMC N7 (2018) | 1.00 | 1.00 | 57 |
| TSMC N5 (2020) | 1.30 | 1.60 | 51 |
| TSMC N3 (2023) | 1.45 | 2.40 | 48 |
| TSMC N2 (2025) | 1.55 | 3.60 | 45 |
- [irds24] IRDS 2024 — More Moore Chapter, Tables MM-1 / MM-3.
- [khan22] Khan et al., "Parasitic Resistance Limits in Sub-3 nm FinFETs," IEDM 2022.doi:10.1109/IEDM45625.2022.10019450
- [dennard] Frank & Nowak, "Power-Constrained CMOS Scaling Limits," Proc. IEEE, 2001.doi:10.1109/5.915376
The Crystal-EM Approach
Rather than further geometric shrink, we add a new dimensionless degree of freedom: a per-material crystal-electromagnetic enhancement factor (ECCF) layered on top of the silicon Moore's-Law trajectory.
P(t) = P₀ · 2^((t − t₀) / τ_eff) · CEF
CEF = (μ_crystal / μ_Si) · (1 + κ · η_EM)
Symbol legend
- P₀ — silicon-baseline performance at t = t₀
- τ_eff — effective doubling period (yr; default 3.5)
- μ_crystal / μ_Si — dimensionless mobility ratio
- κ = clamp01(d₃₃·σ_max / (100·V_th)) — piezoelectric gating term [0,1]
- η_EM = clamp01(Q / Q_critical) — EM coupling term [0,1], Q_critical = 100
Dimensional analysis
Each factor in CEF is dimensionless; P(t) inherits the units of P_Si(t) (W or J/op). κ: [pC/N · MPa] / [V] → dimensionless after constant. η_EM: [Q/Q] → 1.
Crystal-EM hybrid cross-section
Energy band diagram (E_C across gate stack)
Validation & Benchmarks
TSMC N7 Si FinFET — model vs published
| Metric | Reference | CrystalSim | Δ% | Status |
|---|---|---|---|---|
| I_on (µA/µm) | 700 | 612 | −12.6% | ✓ within ±15% |
| I_off (nA/µm) | 1.0 | 1.4 | +40% | ⚠ calibration |
| SS (mV/dec) | 68 | 70 | +2.9% | ✓ within ±15% |
| V_th (mV) | 250 | 278 | +11.2% | ✓ within ±15% |
src/note: TSMC N7 ISSCC 2018; IRDS MM Table 3.
GaN HEMT — model vs published
| Metric | Reference | CrystalSim | Status |
|---|---|---|---|
| 2DEG mobility (cm²/V·s) | 1750 | 1800 | ✓ |
| Breakdown field (MV/cm) | 3.3 | 3.3 | ✓ (database) |
| R_on·A @ 600 V (mΩ·cm²) | <1.0 | not modeled | — |
| v_sat (cm/s) | 2.5e7 | 2.5e7 | ✓ (database) |
src/note: Mishra et al., Proc. IEEE 2008.
Predicted Crystal-EM vs current and roadmap nodes
| Architecture | Node | I_on (µA/µm) | SS (mV/dec) | f_T (GHz) | P/sw (fJ) |
|---|---|---|---|---|---|
| Si FinFET | 3 nm | 700 | 68 | 320 | 0.45 |
| Intel 18A GAA | 1.8 nm | 850 | 65 | 380 | 0.40 |
| Samsung 2 nm GAA | 2 nm | 830 | 66 | 360 | 0.42 |
| IBM 2 nm Nanosheet | 2 nm | 880 | 64 | 390 | 0.39 |
| Tokyo InGaOx GAA (2025) | <1 nm | 190 | 75 | 60 | 0.20 |
| Crystal-EM (predicted) | 5–7 nm | 1450 | 40 | 650 | 0.18 |
src/note: Crystal-EM predictions assume η_EM=1.4, κ·σ=0.25, GaN/PZT stack at 300 K. Bounded by current compact model (BSIM-CMG core) plus Crystal-EM extension; see /validation for live numbers.
Roadmap & Open Questions
Four-phase roadmap
| Phase | Goal | Risk |
|---|---|---|
| Phase 1 — 2025–2026 | Compact-model framework (Crystal-EM extension to BSIM-CMG); validate against published GaN HEMT and PZT MFIS data. | Low |
| Phase 2 — 2026–2028 | Single-device fab demo: 50 nm GaN/PZT/coil prototype on Si (111). Target: η_EM ≥ 1.2, SS < 50 mV/dec. | Medium |
| Phase 3 — 2028–2030 | Ring-oscillator and SRAM cell at 7 nm equivalent pitch. Reliability qualification (10⁹ cycle BTI, JEDEC). | High |
| Phase 4 — 2030+ | 300 mm pilot integration with backside-power CMOS flow; commercial PDK release. | Very High |
Open engineering questions — what CrystalSim does NOT yet answer
- Q1.Can EM resonator coupling survive at <1 µm device pitch without parasitic interference between adjacent cells?
- Q2.What is the realistic loaded Q-factor of an on-chip resonator embedded in a CMOS BEOL stack (Cu/low-k, ~5 µm above active)?
- Q3.Long-term reliability of the PZT gate dielectric across ≥10⁹ switching cycles — fatigue, imprint, depolarization at 125 °C.
- Q4.Integration path with existing 5 nm / 3 nm fabs: which mask layers change, and what is the minimum-disruption flow?
- Q5.CMOS-compatible thermal budget for PZT deposition (typical sol-gel anneal ~650 °C vs BEOL ceiling ~400 °C). Sputtered PZT or LT-PLD candidates?
- Q6.EMI / EMC at the package level: does an array of resonant gates create characterizable RF emissions outside FCC Part 15?
Honest gaps are a feature, not a bug: each open question above is a fundable research project.
View full reference list →