CRYSTALSIM

initializing lattice

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// references

Engineering Brief — Citations

Every paper, standard, and dataset referenced in the 4-page brief. DOIs link to the canonical record.

  1. [irds24]IEEE IRDS™ 2024 Edition — More Moore Chapter.
    https://irds.ieee.org/editions/2024
  2. [khan22]Khan et al., 'Parasitic Resistance Limits in Sub-3 nm FinFETs,' IEDM 2022.
    doi.org/10.1109/IEDM45625.2022.10019450
  3. [frank01]Frank, Dennard, Nowak et al., 'Device Scaling Limits of Si MOSFETs,' Proc. IEEE 89(3), 2001.
    doi.org/10.1109/5.915376
  4. [dennard74]Dennard et al., 'Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions,' IEEE JSSC 9(5), 1974.
    doi.org/10.1109/JSSC.1974.1050511
  5. [sze4e]S. M. Sze & K. K. Ng, Physics of Semiconductor Devices, 4th ed., Wiley, 2021.
  6. [mishra08]Mishra, Parikh, Wu, 'AlGaN/GaN HEMTs — An Overview of Device Operation and Applications,' Proc. IEEE 96(2), 2008.
    doi.org/10.1109/JPROC.2007.911060
  7. [wang07]Z. L. Wang, 'Piezotronic Effect in Wurtzite Materials,' Adv. Mater. 19(6), 2007.
    doi.org/10.1002/adma.200602918
  8. [nomura04]Nomura et al., 'Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amorphous Oxide Semiconductors,' Nature 432, 2004.
    doi.org/10.1038/nature03090
  9. [tokyo25]University of Tokyo, 'Sub-1 nm InGaOx Channel GAA at VLSI Symposium,' 2025.
  10. [tsmcn7]TSMC, '7 nm CMOS Technology Featuring Multi-Vt Devices,' ISSCC 2018.
  11. [intel18a]Intel, 'Intel 18A Process — RibbonFET + PowerVia,' VLSI 2024.
  12. [ibmns2]IBM Research, '2 nm Nanosheet Technology,' IEDM 2021.
  13. [jedec]JEDEC JESD22-A108 (BTI), JESD92 (TDDB Weibull), JESD28 (HCI Test Methods).