Moore's Law held for 60 years because engineers kept finding clever ways to make transistors smaller. But now, transistors are approaching the size of individual atoms. At this scale, five physical barriers are converging to make further shrinking impractical — or impossible.

Barrier 1: Quantum Tunneling

Key Concept

Quantum Tunneling

A quantum physics phenomenon where electrons can pass through barriers they shouldn't be able to cross. At the atomic scale (below 3nm gate lengths), electrons have a probability of 'teleporting' through the transistor gate barrier, causing current to flow even when the transistor is supposed to be OFF.

A tennis ball through a wall

Imagine throwing a tennis ball at a wall. Normally it bounces back. But if the wall is only a few atoms thick, quantum mechanics says there's a chance the ball passes straight through — like a ghost through a wall. That's quantum tunneling. When your transistor gate is 15 atoms wide, electrons start ghosting through it.

Diagram · Quantum tunneling vs gate length

interactive

Gate Length

20 nm

1 nm3 nm10 nm100 nm

Tunneling probability per electron1.8%

Drag the slider. At 100nm the wall is thick — particles bounce back. At 1nm it's thin enough that electrons start ghosting through.

Barrier 2: Leakage Current

Key Concept

Leakage Current

Unwanted current that flows through a transistor even in its OFF state. Caused by quantum tunneling and extremely thin gate oxide layers. Leakage wastes power and generates heat, reducing both efficiency and battery life.

Leakage current is directly tied to quantum tunneling. As gates get thinner, more electrons tunnel through when they shouldn't, creating a constant trickle of wasted current. In modern processors, leakage power can account for 30–50% of total chip power consumption — electricity doing nothing useful.

Barrier 3: Heat

Key Concept

Thermal Dissipation

The challenge of removing heat from a chip. As transistors are packed more densely, they generate more heat per unit area. Modern processors can exceed 100 W/cm², which is hotter than a kitchen stovetop. If heat can't be removed fast enough, the chip throttles its speed or fails.

Barrier 4: Cost

Building chips at 3nm and below requires Extreme Ultraviolet (EUV) lithography machines that cost over $200 million each. The newest High-NA EUV tools cost nearly $400 million. A single chip fabrication facility (called a 'fab') costs $20–30 billion to build. Only three companies in the world — TSMC, Samsung, and Intel — can even attempt to manufacture at these scales.

Barrier 5: Dennard Scaling Collapse

Key Concept

Dennard Scaling

The observation (by Robert Dennard, 1974) that as transistors shrink, they use proportionally less power — meaning you could pack more in without increasing total power. This relationship broke down around 2004. Since then, smaller transistors no longer automatically mean better power efficiency.

An apartment tower that can't add more floors

Imagine building an apartment tower. For decades, each new floor you added was thinner but lighter, so the building could keep growing without the foundation cracking. Then around 2004, the rule changed — each new floor weighs the SAME as the old ones. Now every floor you add risks crushing the ones below. That's the Dennard scaling collapse.

Checkpoint · +5 XP

Which barrier causes current to flow even when a transistor is OFF?

These five barriers aren't engineering problems that cleverness can solve. They are physical limits rooted in quantum mechanics and thermodynamics. Making transistors even 10% smaller won't fix them — in some cases, it makes them worse. That's why the industry needs a fundamentally different approach.

Try It Yourself

Watch tunneling in action

Open the Transistor Sim. Select Planar FET with Silicon channel. Set gate length to 1nm. Look at the leakage current value — it's enormous compared to 3nm or 5nm. That's quantum tunneling in action.

Open Transistor Sim

Lesson Summary

Five physical barriers are converging — not engineering problems, real physics.
Quantum tunneling lets electrons leak through gates only ~15 atoms thick.
Leakage current can waste 30–50% of total chip power as pure heat.
EUV lithography costs $200M+ per machine; only TSMC, Samsung, and Intel can manufacture at 3nm.
Dennard scaling broke around 2004 — smaller no longer automatically means more efficient.

Test Your Knowledge · +50 XP

What is quantum tunneling?

What percentage of chip power can leakage current waste?

How much does an EUV lithography machine cost?

When did Dennard Scaling break down?

How many companies can currently manufacture at 3nm scale?