A crystalline channel in a real GAA device

Pillar 1 of the thesis (crystal channels) needed a clean experimental proof in a modern transistor architecture — not a nanowire on a glass slide, but a real gate-all-around device of the kind being deployed at 3 nm and 2 nm nodes. The University of Tokyo published exactly that in 2025: an InGaOx gate-all-around FET with a crystalline oxide channel grown by atomic-layer deposition.

Key Concept

Gate-All-Around (GAA)

A transistor architecture where the gate fully encircles the channel (typically a stack of nanosheets or a nanowire). GAA gives the gate maximum electrostatic control, suppresses leakage at small Lg, and is the industry's planned successor to FinFET below 3 nm.

Key Concept

Atomic Layer Deposition (ALD)

A chemical thin-film growth technique that deposits one atomic layer per cycle. Conformal, sub-nm thickness control. Critical for growing the wrap-around dielectric and channel of a GAA — and the only practical way to grow a crystalline oxide channel monolayer by monolayer.

Key Concept

Crystalline Oxide

An oxide semiconductor (e.g. InGaOx, IGZO, In₂O₃) grown with long-range atomic order rather than as an amorphous film. Crystalline oxides exhibit higher carrier mobility, lower trap density, and better bias-stress stability than their amorphous cousins.

Diagram · From planar to GAA — Tokyo's wrap angle

interactive

Gate wrap angle: 360°

Planar (0°)FinFET (180°)GAA (360°)

Gate fully encircles the channel (GAA) — Tokyo's InGaOx device. Best electrostatic control.

I_on (drive current)1.00× ref

I_off (leakage)20%

Tokyo 2025 InGaOx GAA: μ = 44.5 cm²/V·s · stable 3 hr under stress · ALD-grown crystalline channel

Slide from 0° (planar) → 180° (FinFET) → 360° (GAA) and watch I_on rise while leakage falls.

Pinching a garden hose

A planar gate is pinching a hose with one finger; a FinFET pinches with three; GAA pinches with your whole fist. Tokyo's contribution: the *hose itself* is now a single crystal, so when the fist relaxes, water flows fast and clean.

Checkpoint · +5 XP

Why does GAA architecture matter for crystal-channel research?

The 2025 Tokyo numbers in plain language.

- μ = 44.5 cm²/V·s — about 4× the mobility of amorphous IGZO (the current production oxide-TFT material) and only ~3× lower than crystalline silicon. For an oxide GAA device this is a record. - Stable 3 hours under bias stress — historically, oxide channels degrade rapidly. ALD-grown crystalline order suppresses the trap states that cause drift. - Wafer-compatible flow — uses standard ALD, standard etch, standard lithography. No exotic processing.

What this proves for the thesis: crystal channels are not just a lab curiosity on bent nanowires — they survive a full GAA process and behave well. Pillar 1 is no longer aspirational.

Try It Yourself

Run a Tokyo Crystal-Oxide template

In the Hybrid Designer, load the 'Tokyo Crystal Oxide' template and run an I-V sweep. Compare the curves to the silicon planar baseline at the same channel length.

Open Hybrid Designer

Lesson Summary

In 2025, the University of Tokyo demonstrated a crystalline InGaOx gate-all-around transistor.
Channel grown atomic layer by atomic layer (ALD) — fully crystalline, not amorphous oxide.
Measured mobility: 44.5 cm²/V·s. Stable for 3 hours under continuous bias stress.
This is the missing experimental proof that a crystal channel works in a real, fabricated, GAA transistor — not just a nanowire.

Test Your Knowledge · +60 XP

What architecture did the Tokyo 2025 device use?

How was the InGaOx channel grown?

Reported mobility:

Why does crystalline (vs amorphous) oxide matter?

Which thesis pillar does the Tokyo result validate?