A new scaling law for the post-Moore era
Moore's Law described one specific kind of progress: how many transistors fit on a chip when you make each one smaller. It worked for fifty years, then physics hit back — quantum tunneling, leakage, heat. Simon's Law describes a different kind of progress: how chip performance scales when you instead improve the quality of the crystal medium and the efficiency of the electromagnetic coupling driving it.
Formally:
> P(t) = P_Si(t) · CEF > > P_Si(t) = P₀ · 2^((t − t₀)/τ_eff) > CEF = (μ_crystal/μ_Si) · (1 + κ · η_EM)
where - P_Si(t) — silicon-equivalent trajectory (τ_eff > 2 yr, typically 3–5 post-2020) - μ_crystal/μ_Si — mobility ratio (dimensionless material multiplier) - κ — piezo gating contribution = clamp01(d₃₃·σ_max/V_th) - η_EM — EM coupling efficiency = clamp01(Q/Q_critical), Q_critical ≈ 100 - ECCF = κ · η_EM (both clamped to [0,1] before multiplication)
The key structural difference from Moore's Law: silicon's curve is amplified by a quality factor (CEF) you can keep improving without shrinking anything.
The key insight (memorise this):
> Moore's Law scales with SIZE. (Make things smaller.) Size has a physical floor — you cannot make a transistor smaller than an atom. > > Simon's Law scales with QUALITY. (Make crystals purer and EM coupling more efficient.) Quality has no equivalent floor; the theoretical ceiling on d₃₃ and Q is far above any value reported today.
That asymmetry is why a quality-based scaling law could outlast a size-based one.
- Simon's Law: P(t) = P_Si(t) · CEF, with CEF = (μ_crystal/μ_Si)·(1 + κ·η_EM).
- P_Si(t) = P₀ · 2^((t−t₀)/τ_eff) with τ_eff > 2 yr (post-2020 deceleration).
- ECCF = κ · η_EM (both clamped to [0,1]) — dimensionless by construction.
- Three independent levers: crystal quality (d₃₃), engineering (σ_max, V_th, Q).